1. Field Of The Invention
This describes a self calibrating timing circuit and more particularly a timing circuit that uses a ratio of two capacitors to generate sub-cycles of a main clock frequency to create timing edges that are independent of the main clock frequency.
2. Description Of The Prior Art
Often in complex digital systems such as microprocessors it is necessary to have multiple timing edges upon which all the sequential events are based. In the past there has been used various techniques to produce such timing edges by delaying one or more edges of a reference clock signal, such as using RC circuits or delay lines. The prior art circuits however had problems with noise and accuracy due to sensitivity to temperature and process variations in the making of the devices comprising the delay circuit. These problems caused the delay generated to vary. Such variations can cause digital logic systems to malfunction. Still, other prior art systems used voltage controlled oscillators to provide control voltages to the controlled stages of tapped delay lines or used multiple capacitors that were varied with switches. Such other systems encountered similar problems and had undesirable side effects.
Thus, in microcircuitry requiring precision compact, low power timing circuits, a need has continually existed for stable, noise free, low power and easily variable timing circuits.